Samsung Electronics (Aug 2022 - Aug 2023)

Senior Engineer - System Architecture and Digital Design

Worked on 3D IC test chip projects at Samsung's Foundry Business Unit.

Imagination Technologies (Jul 2021 - Aug 2022)

Hardware Engineer - Design Automation and RTL design

Worked on RTL design and fixes, lint, cdc, synthesis, power analysis, equivalence check and entire design flow as part of automotive Ethernet Processing IP (layer 2 switch and layer 3 routers) team. Worked on many internal Design Automation tools including FMEDA (Failure modes, effects, and diagnostic analysis) generator which was being used in all automotive IPs. Worked on ISO 26262 safety critical analysis.

FPGA Implementation of CRAFT Algorithm (May-Aug 2020)

Research intern @ TCS Research & Innovation

Suggested FPGA based architectures and automated implementation of CRAFT, a CNN based text detection algorithm on FPGA for real time inference.

Application of this work could be in self-driving vehical to detect real time scene text.

Design Space Exploration of Approximate Prefix Adders (May-Jul 2020)

Research intern @ Vienna University of Technology (TU Wien)

Mentor: Prof. Muhammad Shafique

Automated complete design space exploration to extract all possible approximate prefix adders from 4 different prefix trees, Kogge Stone, Brent Kung, Han Carlson and Ladner Fischer Adder. More than 1.4 Million adder configurations are generated (Verilog), tested, synthesized and the accuracy matrix calculated.

Accuracy Configurable Arithmetic Circuits (May-Jul 2019)

Research intern @ IIT Ropar

Mentor: Dr. Neeraj Goel

Studied various existing approximate binary adders and multipliers. Proposed An Accuracy Configurable Adder and An Accuracy-Configurable Rounding-Based Multiplier. Compared proposed algorithms with state of the art algorithms using different performance and error matrix.