Alish Kanani

About Me

Welcome to my page!

Hi, I am a final year undergraduate student at the Department of Electrical Engineering, Indian Institute of Technology(IIT) Jodhpur, India. I am intrested in the areas of Digital Circuit Design, Approximate Circuits, Hardware Acceleration, High Performance Computing etc.

I am currently looking for the full time engineering roles starting from June 2021.

Resume Email id

Skills

Languages

C
Python
MATLAB
Perl(Basic)
Verilog
HLS

Softwere

Vivado
Vitis AI
Vitis HLS
Synopsys DC
Cadence Virtuoso(Basic)
Simulink

Others

CNN
FPGAs
Arduino
LaTex
NodeMCU
Beaglebone
Photoshop

Projects

B.Tech Project: TCS R&I | Sep-Nov 2020 | Dr. Harshit Agarwal

Automated the Verilog generation of decision tree-based LightGBM for FPGA implementation and made the LightFPGA library which performs all the required steps for Verilog Generation and testing form extracted LightGBM classification model. Around 700 to 1000X speedup achieved for different data-sets on FPGA.

Technologies: Python | Verilog | Alveo Accelerator Card

Self Project | Sep-Dec 2020

CRAFT Incorporating dynamics of Cricket into ML based regression model to get a realistic & fair value of revised target score. Cleaned the dataset of over 1900 ODI and 1700 T20 matches.

Technologies: Python | Regression prediction

Internship: TCS R&I | May-Aug 2020

CRAFT is a CNN based algorithm which makes bounding box around the text in natural image. I suggested different FPGA implementation methodology to get speed up in the inference and achieved 3 to 100X speedup using different approaches.

Technologies: Vitis AI | Vitis HLS | ONNX | Netron | Alveo Accelerator Card

Internship: Tu Wien | May-July 2020 | Prof. Muhammad Shafique

Automated complete design space exploration for the approximate parallel prefix adders namely Kogge Stone Adder, Brent Kung Adder, Han Carlson Adder and Ladner Fischer Adder. More than 1.4 Million adder configurations are tested, synthesized and the accuracy matrix generated.

Technologies: Python | Verilog | ABC synthesis tool | Synopsys DC

Internship: IIT Ropar | May-July 2019 | Dr. Neeraj Goel

Studied various existing approximate binary adders and multipliers. Proposed An Accuracy Configurable Adder and An Accuracy-Configurable Rounding-Based Multiplier. Compared proposed algorithms with state of the art algorithms in Synopsys Design Compiler and in octave.

Technologies: Verilog | Synopsys DC | Octave

Inter IIT/IICDC Project | Sep 2019 - Dec 2019

Developed a low-cost, user-friendly, IoT enabled, head-phone sized tympanometer that detects middle ear problem. Made business model for IICDC 2019 and Inter IIT 2019.
Business Video, Technical Video
Technologies: NodeMCU

B.Tech Project | Jan 2019 - Apr 2019 | Dr. Shree Prakash Tiwari

Studied six different algorithms to add two binary numbers Compared delay, area and power of these algorithms in Xilinx-ise. Code

Technologies: Verilog | Xilinx ISE

Gymkhana Project | Sep 2018 - May 2019

Developed an FPGA based encryption-decryption engine to facilitate speed up AES encryption. Matlab Code

Technologies: MATLAB | Verilog

IICDC Project | Aug 2018 - May 2019

Designed and developed a cost effective wearable device to assist visually impaired in indoor navigation without relying on GPS or internet connectivity using 9-axis IMU and dead reckoning. Business Video, Technical Video

Technologies: Beaglebone | IMU

Publications

A. Kanani, J. Mehta and N. Goel, “ACA-CSU: A Carry Selection Based Accuracy Configurable Approximate Adder Design”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020.
Paper, Presentation
R. Bhattacharjya, A. Kanani and N. Goel, “ReARM: A Reconfigurable Approximate Rounding-Based Multiplier for Image Processing”, 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020.
Paper, Presentation, Video