Alish Kanani

Alish Kanani

PhD Candidate at the UW-Madison

Research Summary

My research develops efficient AI systems through cross-layer co-design of models, runtime policies, accelerators, chiplets, and packaging. See my Google Scholar profile for the complete publication list.

Multi-Chiplet Architectures

Emerging 2.5D and 3D multi-chiplet architectures create coupled challenges across temperature, power delivery, data movement, workload mapping, and hardware specialization. My work in this area spans heterogeneous chiplet design-space exploration for dynamic LLM serving (HYDRA), voltage-droop-aware control for PIM chiplets (ReVolt), multi-fidelity thermal modeling (MFIT), thermally-aware scheduling (THERMOS), co-simulation (CHIPSIM), energy-efficient inference architectures (HeMu), and inter-chiplet communication for hybrid LLMs (LEXI).

Together, these projects improve how chiplet-based systems are modeled, scheduled, and architected for efficient AI inference under thermal, bandwidth, and energy constraints.

2.5D chiplets 3D chiplets
64 chiplets heatmap

Related Published Papers

  1. Jiahao Lin, Alish Kanani, Sangwan Lee, Jaehyun Park, and Umit Y. Ogras, “HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads,” ESWEEK (CASES) - IEEE TCAD, 2026. Paper, Code
  2. Vibhanshu Sharma, Alish Kanani, Miao Sun, Janardhan Rao Doppa, Umit Y. Ogras, and Partha Pratim Pande, “ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures,” ESWEEK - IEEE TCAD, 2026. Paper
  3. Miao Sun, Alish Kanani, Kaushik Shroff, and Umit Y. Ogras, “LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs,” DAC, 2026. Paper
  4. Lukas Pfromm, Alish Kanani, Harsh Sharma, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras, “CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems,” IEEE OJ-SSCS, 2025. Paper, Code
  5. Harsh Sharma, Alish Kanani, Janardhan Rao Doppa, Umit Y. Ogras, and Partha Pratim Pande, “HeMu: Energy-Efficient DNN Inferencing via Heterogeneous-Multi-Chiplet Architectures,” IEEE TCAD, 2025. Paper
  6. Alish Kanani, Lukas Pfromm, Harsh Sharma, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras, “THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures,” ESWEEK - ACM TECS, 2025. Paper, Code
  7. Lukas Pfromm*, Alish Kanani*, Harsh Sharma, Parth Solanki, Eric Tervo, Jaehyun Park, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras, “MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures,” ACM TODAES, 2025. Best Paper Award; Editor’s Pick. Paper, Blog, Code
  8. Jaehyun Park, Alish Kanani, Lukas Pfromm, Harsh Sharma, Parth Solanki, Eric Tervo, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras, “Thermal Modeling and Management Challenges in Heterogeneous Integration: 2.5D Chiplet Platforms and Beyond,” VTS, 2024. Paper

* Equal contributions

LLM and ML Acceleration

My accelerator and runtime research targets efficient execution of modern ML models across edge and datacenter systems. APEX adaptively prefetches experts for memory-efficient edge MoE inference; DUET disaggregates hybrid Mamba-Transformer inference across prefill/decode-specific packages; and eMamba accelerates Mamba models at the edge. My earlier work explored automated FPGA acceleration for tree-based ML models through LightFPGA.

DUET disaggregated accelerator system

Related Published Papers

  1. Alish Kanani, Layan Badawi, and Umit Y. Ogras, “APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference,” ESWEEK (CODES) - IEEE TCAD, 2026. Paper
  2. Alish Kanani, Sangwan Lee, Han Lyu, Jiahao Lin, Jaehyun Park, and Umit Y. Ogras, “DUET: Disaggregated Hybrid Mamba-Transformer LLMs with Prefill and Decode-Specific Packages,” DAC, 2026. Paper, Code
  3. Jiyong Kim, Jaeho Lee, Jiahao Lin, Alish Kanani, Miao Sun, Umit Y. Ogras, and Jaehyun Park, “eMamba: Efficient Acceleration Framework for Mamba Models in Edge Computing,” ESWEEK - ACM TECS, 2025. Paper
  4. Alish Kanani*, Swar Vaidya*, and Harshit Agarwal, “LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning Applications,” VDAT, 2021. Paper, Slides, Code

Runtime Optimization using Machine Learning

Dynamic runtime optimization focuses on balancing latency, energy, temperature, and resource utilization in heterogeneous computing systems. My work in this area includes THERMOS, which performs thermally-aware multi-objective scheduling for AI workloads on heterogeneous multi-chiplet PIM architectures, and runtime monitoring techniques that make ML-based schedulers more robust for Domain-Specific SoCs (DSSoCs). Together, these frameworks improve performance and energy efficiency while managing dynamic workloads, resource contention, and thermal constraints.

robust task scheduling

Related Published Papers

  1. Alish Kanani, Lukas Pfromm, Harsh Sharma, Janardhan Rao Doppa, Partha Pratim Pande, and Umit Y. Ogras, “THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures”, In ESWEEK - TECS, 2025. Paper, Code
  2. Alper A. Goksoy, Alish Kanani, Satrajit Chatterjee, and Umit Y. Ogras, “Runtime Monitoring of ML-Based Scheduling Algorithms Toward Robust Domain-Specific SoCs” ESWEEK- TCAD, 2024. Paper

Related Patent

Umit Y. Ogras, Ahmet Alper Goksoy, and Alish Kanani, “Runtime Monitoring of Machine Learning-Based Scheduling Algorithms Toward Robust Domain-Specific Systems-on-Chip,” U.S. Patent Application US20260093522A1, 2026. Patent

Approximate Computing and Applications

Approximate computing trades accuracy for efficiency, making it a perfect fit for energy-constrained systems and error-resilient applications.

I worked on several exciting projects in this area, such as developing ReARM, a reconfigurable approximate multiplier, and ACA-CSU, a carry-selection-based adder, to optimize power and performance for tasks like image processing. My work extended to ApproxBioWear, targeting efficient arithmetic for wearable biomedical devices, and even explored the feasibility of approximation in communication systems. Most recently, Ellora applied these concepts to create low-power radar processors, blending approximate computing with advanced OFDM techniques.

aca_csu approx_bio
approx_comm approx_radar

Together, these projects showcase a broad application of approximation, pushing the boundaries of energy efficiency across diverse domains.

Related Published Papers

  1. Rajat Bhattacharjya, Alish Kanani, A Anil Kumar, Manoj Nambiar, M Girish Chandra, Rekha Singhal, “Ellora: Exploring Low-Power OFDM-based Radar Processors using Approximate Computing” – LASCAS 2024. Paper
  2. Ish Kool, Alish Kanani, Rajat Bhattacharjya, “Approximating Communication Systems: Reality or Fantasy?” – HiPC 2021. Paper,Slides
  3. Alish Kanani, Rajat Bhattacharjya and Dip Sankar Banerjee, “ApproxBioWear: Approximating Additions for Efficient Biomedical Wearable Computing at the Edge” – EMBC 2021. Paper, Slides
  4. Alish Kanani, Jigar Mehta and Neeraj Goel, “ACA-CSU: A Carry Selection Based Accuracy Configurable Approximate Adder Design” – ISVLSI 2020. Paper, Slides, Code
  5. Rajat Bhattacharjya, Alish Kanani and Neeraj Goel, “ReARM: A Reconfigurable Approximate Rounding-Based Multiplier for Image Processing” – VDAT 2020. Paper, Slides